1. Field of the Invention
The present invention relates to a metal semiconductor device such as a GaAs metal semiconductor field effect transistor (MESFET) and a method for producing the same.
2. Description of the Background Art
Nowadays, in a supercomputer or a high frequency communications apparatus, high-speed field-effect transistors (FETs) employing a metal-semiconductor substrate such as GaAs, InP or the like having a double to several times higher electron mobility than that of silicon (Si) at the normal temperature, are frequently used. In these FETs, a Schottky gate type GaAs metal-semiconductor field-effect transistor (MESFET) is known. A conventional manufacturing process of this GaAs MESFET is schematically shown in FIG. 1.
In FIG. 1a, an active region 11.sub.1 is formed on a semi-insulating GaAs substrate 10 by an ion implantation and a heat treatment for activating it.
Then, in FIG. 1b, a tungsten nitride (WNx) film is deposited on the entire surface of the substrate 10 including the active region 11.sub.1 by, for example, a sputtering, and the WNx film is selectively etched to form a gate electrode 12 on the active region 11.sub.1. The film deposited by the sputtering is a polycrystal composed of crystal grains 12.sub.1 with crystal grain boundaries 12.sub.2 therebetween. There exist gaps in the crystal grain boundaries 12.sub.2 between the crystal grains 12.sub.1. Similarly, there are crystal grain boundaries with gaps in a polycrystalline tungsten nitride film, molybdenum nitride film, iridium nitride film, tungsten silicide film, molybdenum silicide film or nitride, silicide or siliconitride film of a high melting point metal such as tungsten siliconitride or the like formed by a CVD method or an EB evaporation method.
In FIG. 1c, by using a resist having open windows and the gate electrode 12 as masks, impurity doping regions 13.sub.1 and 14.sub.1 to be source and drain regions are formed in both side portions of the gate electrode 12 by an impurity implantation.
In FIG. 1d, after removing the resist, while using an arsine (AsII.sub.3) atmosphere with a high pressure so as to restraining the release of arsenic (As) having a high vapor pressure from the substrate, the impurity doping regions 13.sub.1 and 14.sub.1 are activated by, e.g., a capless annealling at a temperature of approximately 820.degree. C. to form respective source and drain regions 13.sub.2 and 14.sub.2 which self-aligns to the gate electrode 12. At the same time, the active region 11.sub.1 is converted to a channel region 11.sub.2 connecting the source and drain regions 13.sub.2 and 14.sub.2.
The capless annealing for use in this embodiment, which is different from another capless annealing to be carried out when a thick insulating film is formed on the entire surface of the substrate including the gate electrode 12, is a superior annealing method which imparts no stress to the gate electrode 12 and the surface of the substrate 12 during the high temperature thermal treatment.
However, in such a capless annealling, although a high pressure is applied to the atmosphere during the thermal treatment so that the arsenic does not release from the substrate in conformity with the phase equilibrium of the semiconductor region (except the gate electrode region) directly exposing to the atmosphere, the phase equilibrium of the semiconductor region having the gate electrode 12 thereon is different from that of the region directly exposing to the atmosphere. Accordingly, the elements such as As having a high vapor pressure in the channel region 11.sub.2 can readily release to the atmosphere through the crystal grain boundaries 12.sub.2 depending on the heat treatment conditions such as pressure, temperature and so forth.
As a result, the crystallization of the channel region 11.sub.2 of the interface between the channel region 11.sub.2 and the gate electrode 12 is disordered, and thus the Schottky characteristics between the channel region 11.sub.2 and the gate electrode 12 are deteriorated, as well as a threshold voltage dispersion is caused. As explained above, in the capless annealing, it is difficult to conduct the thermal treatment of the region having the gate electrode and the region having no gate electrode at the same time.